Rahul

Education

Present

B.Sc. Engineering Undergraduate

Department of Electronic & Telecommunication Engineering (ENTC)

University of Moratuwa, Sri Lanka

Specializing in core analog electronics, embedded systems, RF and digital systems.

2009 to 2022 (Graduated)

G.C.E Advanced Level

T/R.K.M Sri Koneswara Hindu College (Mathematics, Physics, Chemistry, General English)

4As / 89th in the country / z-score of 2.69

My Projects

300W Pure Sine Wave Inverter

Designed a custom pure sine wave inverter from scratch using EG8010 chip using 2 seperate 2-layer PCBs, with custom metal enclosure.

Altium Designer LTSpice SOLIDWORKS Power Electronics

GitHub Repository →

Automatic Analog Solar Tracker

Purely made out of analog electronic components without utilizing any digital components with PID controller, built on a 3-layer PCB with custom enclosure.

Altium Designer LTSpice SOLIDWORKS Analog Electronics

GitHub Repository →

Class D High Efficiency Audio Amplifier

A high efficiency Class D Audio amplifier featuring tone controller, high frequency PWM stage and a custom gate driving stage.

Altium Designer LTSpice Analog Electronics

GitHub Repository →

FPGA UART Transceiver with AXI4-Stream

Implemented a UART transceiver on an Altera Cyclone IV FPGA featuring 8x oversampling for noise immunity and frame/overrun error detection.

Verilog Quartus Prime FPGA ModelSim

GitHub Repository →

16 Bit Single Bus CPU Design

Designed and verified a single bus CPU with ADD and LOAD instructions.

SystemVerilog Digital System Design CPU Design

GitHub Repository →

Systolic Array Matrix Multiplier — Arithmetic IP

Part of an ongoing Arithmetic IP collection: a parametrized, synthesizable NxN systolic array in SystemVerilog, verified end-to-end at N=3 with a hand-computed matrix product sanity check.

SystemVerilog Arithmetic IP RTL Design

GitHub Repository →

My PCB designs

Custom Multi-Layer PCBs designed on Altium Designer.

3D Render

Layout

Analog Solar Tracker

4-Layer

A 3-layer PCB consisting of only analog components (OPAMPs and Transistors).

Altium Analog Electronics

Schematic → Fabricated

3D Render

Layout

Class D Amplifier

2-Layer

Fully functional, class D amplifier with high efficiency made with custom gate driver, PWM generation and tone controller.

Altium Analog Electronics

Schematic → Fabrication

3D Render

Layout

Inverter Controller

2-Layer

Controller board of the 300W Pure Sine Wave Inverter consisting of EG8010 ASIC chip for SPWM generation.

Altium Power Electronics

Schematic → Fabricated

Ongoing Projects

Smart Digital Power Analyzer

WIP

Designing an embedded power analyzer with an isolated Analog Front-End (AFE) and real-time DSP firmware.

Circuit Designing 10%

Power Electronics Embedded Systems

CNN Accelerator with RISC-V SoC Integration

WIP

3-member team project: FPGA-based CNN inference accelerator integrated as a memory-mapped peripheral with a RISC-V soft-core. Own the Dataflow & Memory pillar (line buffers, sliding window, padding).

Core components built & verified 25%

SystemVerilog Digital System Design

RISC-V RV32I Single-Cycle CPU

WIP

Building a single-cycle RV32I base-ISA CPU in SystemVerilog module by module, each with its own self-checking testbench. PC, Instruction Memory, Register File, Immediate Generator, Control Unit, ALU Control, ALU, Operand Mux and Branch Unit (PC control) are complete and verified.

Building Data Memory next ~80%

SystemVerilog CPU Design

Next Big Thing

Brainstorming new hardware architecture...

Rahul Balakumar

Education

B.Sc. Engineering Undergraduate

G.C.E Advanced Level

My Projects

300W Pure Sine Wave Inverter

Automatic Analog Solar Tracker

Class D High Efficiency Audio Amplifier

FPGA UART Transceiver with AXI4-Stream

16 Bit Single Bus CPU Design

Systolic Array Matrix Multiplier — Arithmetic IP

My PCB designs

Analog Solar Tracker

Class D Amplifier

Inverter Controller

Ongoing Projects

Smart Digital Power Analyzer

CNN Accelerator with RISC-V SoC Integration

RISC-V RV32I Single-Cycle CPU

Next Big Thing

Say Hi!